• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    1520900 Time base corrector SONY CORP 22 Dec 1975 [25 Dec 1974 2 May 1975] 52450/75 Heading H4F Time base errors introduced during recording and reproducing television video signals are removed by writing the signal in digital or analog sample from in a memory unit at a clocking rate which varies in proportion to the time base errors, and then reading out these stored signals at a standard clocking rate. The memory unit comprises a plurality of registers, e.g. three registers each having a capacitor for one line interval of the video signals, having repeating cyclic orders of writing and reading, the video signals read out from each register being recycled or rewritten in the same register. The writing and reading operations are controlled so that writing and reading of any single register is not effected simultaneously. During the occurrence of excessive time base errors the writing or reading period of a register is extended, e.g. from one line interval to two line intervals, so that a line interval signal at the output is either omitted or repeated. If a drop out is detected in the video signal the writing period of a register is extended so as to omit (i.e. deleted due to the recycling action of the register) the line interval containing the drop out from the stored video signals, and during read-out the line interval preceding the deleted line interval is read twice. The write clock pulses, e.g. at three times the subcarrier frequency, are derived from the horizontal sync pulses in the played-back video signals from the magnetic tape recording, and write interval pulses for the three registers are derived from these write clock pulses via a counter and a sequencing counter which latter counter has inhibiting inputs for drop out and excessive time base errors. Read-out from the registers is similarly controlled by a standard clock generator. Instead of being derived from the horizontal sync pulses the write clock pulses may be derived from the subcarrier bursts. To compensate for velocity errors in the played-back video signals the read clock pulses may be modulated during each standard line interval having the standard frequency only at the beginning and end of each standard line interval. The registers may each have the capacity to store two or more line intervals. The registers may comprise random access memories. Instead of storing digitized samples of the video signal in the memory, differentially pulse coded samples may be stored.
    公开号:SU743603A3
    申请号:SU752303261
    申请日:1975-12-25
    公开日:1980-06-25
    发明作者:Татами Мицусиге
    申请人:Сони Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    tator whose outputs are connected to the outputs of the first input switch - and control inputs of the Tti memory block, a demodulator connected by an input to the input of an analog-digital converter and through a series-connected horizontal sync pulse selector, a recording synchronization generator and a second pulse counter to the first input the control unit, the first, second and third outputs of which are connected respectively to the first, second and third inputs of the first and second output switches, the fourth, fifth and sixth outputs of the block. controls are connected respectively to the first / second and third inputs of the first and second input switches, the output of the write synchronization generator is connected to the control input of the first input switch and to the control input of the ADC, whose N outputs are connected through the signal inputs of the second input switch ti, the output of the horizontal sync pulse selector is connected to the second input of the second pulse counter, the output of the first pulse counter is connected to the second input of the control unit, the Detector video signal drops and a loop repetition unit, the input and output of the video signal drop detector are connected respectively to the input of the demodulator and to the third input of the control unit, the inputs of the PS1m unit are connected to the outputs of the repeat cycle unit whose inputs are connected to the DAC inputs, and the control inputs of the block cycle repeats are connected respectively to the first, second and third outputs of the control unit; In addition, the control unit consists of a first pulse counter, the first, second and third outputs of which are the outputs of the control unit, and are respectively connected to the first inputs of the first and second elements, AND, to the first inputs of the third and fourth elements AND, to the first inputs of In addition, the sixth elements and, and the second inputs of the third and sixth elements, the second and fifth elements of the first and fourth elements of the first are connected together to the first, BTOpo.iy and the third outputs of the second needle pulses, the outputs of which are the outputs of the control unit, the outputs of the second, fourth and sixth elements AND through the first element OR are connected to the input of the first inverter, the output of which through the first input of the seventh element AND, to the second input of which is the first input of the control unit, is read pulses connected to the input of the first pulse counter, and the outputs of the first, third and fifth elements AND through the second element OR
    connected to the input of the second inverter, whose output through the first input of the eighth element I, is connected to the input of the second pulse counter, to the second input of the eighth element I, which is the second input of the control unit, recording pulses are fed, the third input of the control unit is connected
    one
    with entry, installation
    trigger
    the first output of which is connected to the second input of the control unit, the second output of the trigger through the third inverter is connected to the third input of the eighth element I.
    Fig. 1 shows a structural electrical circuit of the proposed device; FIG. 2 is a structural electrical circuit of the control unit.
    The synchronization error correction device comprises a memory block 1, the first output switch 2, a digital-to-analog converter 3, a first counter of 4 pulses, a read synchronization generator 5, a second output switch 6, a first input switch 7, a demodulator 8, a 9-line clock selector, a generator 10 write synchronization, second counter 11 pulses, control unit 12, analog-digital converter 13, second input switch 14, video loss detector 15, loop repeater unit 16, in addition, control unit 12 consists of first, second, third, fourth, fifth, sixth, seventh and eighth elements AND 17-24, first and second elements OR 25 and 26, first and second counters 27 and 28 pulses, first, second and third inverters 29 , 30, 31 and trigger 32.
    The device works as follows.
    The input of the demodulator 8 receives periodic information signals - such as reproduced video signals f having sweep errors, which after detection or demodulation post-fall on the analog-to-digital converter 13, then the demodulated video signals go to select 9, separating the signals from them horizontal synchronization to feed them to the generator 10 synchronization record. The write synchronization generator Yu generates recording synchronization pulses of a relatively high frequency, for example, about 10.7 MHz.
    Recording synchronization pulses, having a frequency of approximately 10.7 MHz, are sent to ADC 13 to control the frequency with which ADC 13 samples the instantaneous value of demodulated or detected video signals and converts the last of their original analog form into digital form. Specifically, in response to each sync pulse from the generator 10, the ADC 13 samples the demodulated video signal and converts the latter into a set of parallel digital signals, for example, into digital eight-bit information. Parallel binary signals are fed from the ADC 13 to a set of input key circuits of the input switch 14, each of which consists of a set of AND elements, the number of which is equal to the number of bits constituting the video signals converted into a digital form. The outputs of the input switch 14 are connected respectively to the memory block 1, the memory block 1 contains a set of shift registers, the number of which is equal to the number of bits that compose the video signals converted to digital form. The memory capacitance of the memory unit 1 must be so that, when considering the frequency of the recording synchronization pulses, it is sufficient to memorize one horizontal or line interval of incoming video signals or any number of such horizontal or line intervals. Then, the recording clock pulses are sent from the generator 10 to the counter 11, generating an interval recording pulse, for example, at the end of each horizontal or line interval of incoming video signals, and resetting horizontal synchronization signals from the selector 9 Interval pulses from the counter 11 are fed to the control unit 12 which generates record control signals A1, B1 and C1 in repeated cyclic order, which are respectively fed to the input switch 14 for. determining the sequences in which the required shift registers of memory block 1 are selected for recording consecutive line intervals converted into a digital form of video signals. Then, the clock pulses from the generator 10 are fed to the input switch 7, to the other inputs of which the write control signals A1, B1 and C1 are received, and its outputs are connected to the memory unit 1, respectively. Thus, during the period or interval defined by the signal recording control A1, B1 or C1, digitally converted video signals are passed through the input switch 14 to the memory block 1, while the memory block 1 simultaneously receives write synchronization pulses through the corresponding input switch 7 for recordings of digitized video signals in the shift registers of memory block 1. After being briefly stored in memory 1, video signals converted into digital form are read out of it sequentially and pass through output switch 2, which, like input switch 14, consists of key circuits corresponding to the shift registers of the memory block 1. To control the reading of the video signals stored in the shift registers of the memory block 1, the device has a reference frequency synchronization generator 5, for example, 10.70 Hz, at least at the beginning and end of each reference horizontal or horizontal interval. Such read sync pulses are applied to counter 4, which produces a read interval pulse at the beginning of the reference reference line interval, and read interval pulses are fed to a signal control unit 12, which produces AO, BO and CO read control pulses in a repeating loop order. Such readout control signals AO, VO and CO are sent to output switch 2 to determine the sequence in which the stored video signals from memory register 1 shift registers are read. Then, read synchronization pulses from generator 5 are sent to output switch 6 in parallel and gated control signals reading AO, VO and SB. When the AO, VO or CO readout control signal appears, the corresponding key circuits of the output switches 2 and 6 open, causing the stored video signals to be read out from the shift registers of memory block 1 at the synchronization frequency determined by the read synchronization pulses from the generator 5. The read synchronization pulses from oscillator 5 are then fed to a digital-to-analog converter 3, which also receives a signal from the output of the output switch 2 and which converts video signals read out sequentially from memory 1 from the digital view back to the original analog form, the video signals in an anash signal form being supplied to the exit. Serial line intervals of incoming video signals are recorded in memory block 1 with a synchronization frequency varying in general in accordance with the sweep errors of incoming signals, and video signals are read from memory 1 with a reference synchronization frequency so that video signals received at the output , completely free from scanning errors.
    The key circuits of the loop repetition unit 16 also receive readout control signals from AO, VO and CO. When a read, AO, VO or CO control signal appears to provide readout of signals stored in memory 1, signals read out from it are simultaneously processed. through the loop repetition unit 16 so as to re-record into the memory unit 1. The deposition detector 15 is connected to the input necessary for detecting any loss in the incoming or reproducing video signals and for issuing a signal indicating a fallout to control 12 in response to a drop detection. The inputs of the control unit 12 receive interval write pulses from counter 11 and interval read pulses from counter 4, as well as an outlier signal from the deposition detector 15, which is connected to the state of the trigger trigger 32, the output signal of the trigger 32 is sent through the investor 31 to element AND 24, to which the write pulses of the interval from the output of the counter 11 also arrive. Pulses for reading the interval come from the output of the counter 4 to the element AND 23. Under normal conditions, i.e. when the incoming video signals have relatively small scanning errors, the interval write pulses and interval read pulses, arriving at the inputs of the control unit 12, respectively, pass through And 24 and 23 elements to the corresponding dividing counters 27 and 28 by three. The three stages of the split-28 counter 28 have intermediate terminals for generating three recording control signals A1, B1 and C1, which are removed from the corresponding outputs of the control unit 12. Similarly, the three division-27 counter cascades have three intermediate terminals for processing three AO read control signals, VO and CO at the corresponding outputs of the control unit 12. Recording control signals A1, B1 and C1 under normal conditions are generated sequentially in a repeated cyclic order by counter 28 in response to the output pulse element 24, corresponding to the recording interval pulses input to the control unit 12, as a result of which, each of the recording control signals A1, B1 and C1 will have a positive polarity or have a relatively high level during the time corresponding to line spacing of incoming video signals. Similarly, under normal conditions, the AO read control signals ,. VO and CO are produced sequentially in a repeated cyclic order by counter 27 in response to the output pulses of the element 23, which correspond to the interval read pulses supplied to the input of the control unit 12, each of the AO, VO and CO read control pulses having a positive polarity or a relatively high level for a time equal to the corresponding reference line interval. Further, the counters 28 and 27 are preset so that, under normal conditions, the read control signals for each of the register blocks of memory block 1 are approximately midway between successive write control signals for the same register block.
    However, under conditions other than normal, for example, when incoming video signals have relatively large sweep errors, triggering slits 27 and 28 interval write pulses and interval read pulses through elements 24 and 23, respectively, can lead to a situation where an unsuccessful attempt is made simultaneous write and read operations in one of the register memory blocks 1.
    In order to avoid such simultaneous write and read operations in any of the register blocks of memory 1, control unit 12 also includes three elements AND 19, 21 and 17, which receive, respectively, control signals A1 and VO, control signals B1 and CO, and control signals C1 and AO, and the OR element 26 connecting the outputs of the elements AND 19, 21, 17 with the inverter 30. In addition, the three elements I18, 20 and 22, the outputs of which are connected through the element OR 25 with the inverter 29, are respectively control signals B1 and AO, control signals C1 and VO and control e signals A1 and CO
    权利要求:
    Claims (2)
    [1]
    When a dropout signal does not come to the input of the control unit 12, the trigger 32 outputs a low / level or negative polarity signal to the inverter 31, resulting in the latter giving a positive polarity or high level signal to the AND 24 element. When the control signals the elements And 19, 21, 17, respectively, do not appear simultaneously, at the outputs of any of the elements And 19, 21, 17 no. signal, therefore, the OR element 26 does not generate a signal of relatively high or positive polarity on inverter30, resulting in the latter producing a high level signal or positive polarity on the AND 24 element. Thus, when neither inverter 31 nor inverter 30 receives a signal the prohibition from the trigger 32 or from the element OR 26, respectively, the element AND 24 generates for the corresponding counter 28 each of the interval recording pulses fed to the control unit 12. Similarly, as soon as the control signals, And 18, 20, 22 falling on each of the elements, respectively, do not appear simultaneously, the prohibition of a relatively high level or positive polarity does not come out of the OR 25 element and, therefore, inverter 29 sends a signal of a very high level or positive polarity element 23, as a result of which consecutive interval read pulses arriving at the input of control unit 12 pass through element 23 to start a corresponding counter 27. However, if at the input of control unit 12 connected to input of the setup, a dropout signal appears, trigger 32 is set by it in such a way that it generates a inhibit signal, which causes inverter 31 to send a signal of relatively low level or negative polarity to AND 24, resulting in the latter blocking the passage of interval recording pulses from the input the control unit 12 to the counter 28, suspending the sequencing of the latter until the signal indicating a dropout at the input of the control unit 12 has disappeared and the trigger 32 can be reset next by the pulse of the interval recording, arriving at the input of the pulses of the recording of the control unit 12. Similarly, in the case when the control signals arriving at the elements AND 19, 21, 17, will occur simultaneously, the output signal passing through this the OR element 26 to the inverter 30 causes the latter to signal a relatively low level or negative polarity to the AND 24 element, as a result of which the latter again blocks the sequence of the counter 28 from being recorded by an interval recording pulse which, in the case of the input Lok control 12. Thus, the sequence counter 28 continues zadavats successive interval write pulses coming in at input superfluous as long as no trigger 32 or OR gate 26 does not generate a signal or pulse prohibition sequencer. Similarly, the setting of the sequence of the counter 27 is carried out by successive impulse to read the interval itself, which enters the input of the control unit 12 only until the OR OR 25 element generates a pulse or a prohibition to set the sequence, causing the inverter 29 to send a low-level or negative polarity signal to the AND element 23, i.e., only until such time as the control signals supplied to the elements And 18, 20, 22 are not simultaneously received. Claim 1, A device for correcting synchronization errors in television signals, comprising a memory block, N outputs of which are connected via a first output switch to inputs of a digital to analog converter (D / A converter), the control input of which is connected to the input of a first pulse counter, and output of a read synchronization generator and with the control input of the second output switch, the outputs of which are connected to the outputs of the first input switch and the control inputs of the memory unit, a demodulator connected in one to the input of an analog-to-digital converter (ADC) and through a series-connected horizontal sync pulse selector, a recording synchronization generator and a second pulse counter to the first input of the control unit, the first, second and third outputs of which are connected respectively to the first, second and third inputs of the first and the second output switches, the fourth, fifth and sixth outputs of the control unit are connected respectively to the first, second and third inputs of the first and second input switches, the output of the syn generator Record synchronization. Connected to the control input of the first input switch and to the control input of the ADC, whose N outputs are connected to the memory inputs through the signal inputs of the second input switch, the output of the horizontal sync pulse selector is connected to the second input of the second pulse counter, the output of the first the pulse counter is connected to the second input of the control unit, so that, in order to increase the accuracy of synchronization, a video dropout detector and a loop repeater unit are introduced, with input and output The video signal drop detector is connected respectively to the input of the demodulator and to the third input of the control unit, the inputs of the memory unit are connected to the outputs of the cycle repeater unit, the inputs of which are connected to the DAC inputs, and the control inputs of the cycle repeat unit are connected respectively to the first, second and the third output is by the dami control unit.
    [2]
    2. The device according to claim 1, characterized in that the control unit consists of a first pulse counter, the first, second and third outputs of which are the outputs of the control unit, and are respectively connected to the first inputs of the first and second elements AND, to the first inputs of the third and the fourth elements And, to the first inputs of the fifth and sixth elea.1a, And-, and the second inputs of the third and middle elements And, the second and fifth elements And, the first and fourth and elements And are connected respectively to the first, second and third Leads of the second pulse counter The outputs of which are the outputs of the control unit, the outputs of the second, fourth and sixth elements And through the first element OR are connected to the input of the first inverter whose output through the first input of the seventh element And, to the second input
    which, being the first input of the control unit, read pulses are given, is connected to the input of the first pulse counter, and the outputs of the first, third and fifth elements AND via the second OR element are connected to the input of the second inverter, whose output is through the first input BCX; And, connected to the input of the second pulse counter, to the second input of the eighth element I, which is the second input of the control unit, the recording pulses are fed, the third input of the control unit is connected to the trigger setup input, the first output of which is connected to vto- eye. the control unit, the second trigger output through the third inverter is connected to the third input of the eighth element And
    Sources of information taken into account in the examination
    one,. US patent number 3860952, CL "178-5.1, 1974 (prototype)"
    O
    类似技术:
    公开号 | 公开日 | 专利标题
    SU743603A3|1980-06-25|Device for correcting synchronisation errors in television signals
    US4203076A|1980-05-13|Clock pulse signal generator having an automatic frequency control circuit
    US4602295A|1986-07-22|Recording and reproducing method for video format signal
    US4081826A|1978-03-28|Video time base corrector
    US4313134A|1982-01-26|Track error correction system as for video disc player
    US4212027A|1980-07-08|Time base compensator
    GB2143406A|1985-02-06|Synchronizing signal detecting circuit in a digital signal transmitting system
    US4419699A|1983-12-06|Digital on video recording and playback system
    US4054921A|1977-10-18|Automatic time-base error correction system
    US4437125A|1984-03-13|Digital signal processing method and apparatus
    US4069499A|1978-01-17|Write clock pulse signal generator for digital time base corrector
    US4101939A|1978-07-18|Video synchronizer with velocity compensation
    US4303953A|1981-12-01|Method of positioning reproducing elements and device for carrying out the method
    EP0149566B1|1991-06-12|Apparatus for processing video signals at the time of a special reproduction mode
    JPH06101804B2|1994-12-12|Vertical sync timing signal generator
    US4095259A|1978-06-13|Video signal converting system having quantization noise reduction
    US4486780A|1984-12-04|Sequential data block address processing circuits
    EP0158219B1|1989-09-27|Sync responsive clock generator for digital demodulators
    US4546394A|1985-10-08|Signal reconstruction circuit for digital signals
    GB2202363A|1988-09-21|Controlling time base signals consequent on track jumping in video signal playback
    US3932888A|1976-01-13|Apparatus for modifying the time base of signals
    EP0343724B1|1993-05-05|Device for deriving a sampling rate
    US4325090A|1982-04-13|Device for synchronizing a clock pulse generator with a serial data signal
    US4598169A|1986-07-01|System for detecting a marker signal inserted in an information signal
    US4636877A|1987-01-13|Apparatus for reproducing multiple track digital signals and including timing control of read/write operations
    同族专利:
    公开号 | 公开日
    US4063284A|1977-12-13|
    FR2296334A1|1976-07-23|
    ES443849A1|1977-04-16|
    IT1052625B|1981-07-20|
    DE2557864C3|1980-04-24|
    CA1043900A|1978-12-05|
    AT346926B|1978-12-11|
    ATA979475A|1978-04-15|
    GB1520900A|1978-08-09|
    NL7515027A|1976-06-29|
    DE2557864B2|1979-08-23|
    FR2296334B1|1982-08-27|
    DE2557864A1|1976-07-08|
    AU8771275A|1977-06-23|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3316544A|1963-05-22|1967-04-25|Univ California|Real-time running mean generator|
    US3463874A|1966-05-25|1969-08-26|Minnesota Mining & Mfg|Dropout compensator for ntsc color television|
    US3860952B2|1973-07-23|1996-05-07|Harris Corp|Video time base corrector|JPS555956B2|1975-07-11|1980-02-12|
    US4148079A|1976-08-28|1979-04-03|Robert Bosch Gmbh|Correction of rapid periodic timing errors in the production of tape-recorded color television signals and the like|
    NL190252B|1977-07-14|1993-07-16|Indep Broadcasting Authority|DIGITAL RECORDING AND PLAYING DEVICES.|
    US4188643A|1977-09-26|1980-02-12|U.S. Philips Corporation|Method and arrangement for correcting errors in facsimile transmission|
    GB2008888B|1977-10-27|1982-06-30|Quantel Ltd|Drop-out compensation system|
    SE430455B|1978-04-21|1983-11-14|Nippon Telegraph & Telephone|RECEIVER DEVICE WITH THE FUNCTION TO COMPRESS NOISE DURING Sudden Interruptions|
    DE2822873C3|1978-05-26|1981-03-12|Ted Bildplatten Ag Aeg-Telefunken-Teldec, 6301 Zug|Circuit for reducing dropout interference in a video signal|
    JPS6056358B2|1978-10-26|1985-12-10|Universal Pioneer Corp|
    US4234896A|1978-11-13|1980-11-18|Mitsubishi Denki Kabushiki Kaisha|PCM Recording and reproducing system|
    US4423441A|1979-08-30|1983-12-27|Mitsubishi Denki Kabushiki Kaisha|PCM Record reproducer|
    JPS6133417B2|1979-09-10|1986-08-01|Hitachi Electronics|
    DE3026473C2|1980-07-12|1988-03-03|Robert Bosch Gmbh, 7000 Stuttgart, De|
    JPH056272B2|1981-08-24|1993-01-26|Asahi Optical Co Ltd|
    US4500908A|1982-06-18|1985-02-19|Research And Development Institute For Infosystems, Inc.|Method and apparatus for standardizing nonstandard video signals|
    JPH0348773Y2|1983-04-21|1991-10-17|
    DE3331128A1|1983-08-30|1985-03-14|Dinter, Konrad, Dr., Syracuse, N.Y.|Method of reducing the WOW and FLUTTER values in the sound reproduction of magnetic-tape recordings|
    EP0166975B1|1984-06-01|1993-11-10|Hitachi, Ltd.|Video printer|
    DE3613798A1|1986-04-24|1987-10-29|Grundig Emv|METHOD FOR PROCESSING TELEVISION SIGNALS|
    US4785359A|1986-10-06|1988-11-15|Eastman Kodak Company|Dual purpose memory for time division multiplexing and time base error correction|
    DE3814447C2|1987-04-28|1991-11-07|Canon K.K., Tokio/Tokyo, Jp|
    FR2637143B1|1988-09-27|1993-11-26|Allen Bradley Co|VIDEO IMAGE STORAGE DEVICE|
    JP2757505B2|1989-11-28|1998-05-25|ソニー株式会社|Time axis correction device|
    US5199576A|1991-04-05|1993-04-06|University Of Rochester|System for flexibly sorting particles|
    US5347322A|1991-07-09|1994-09-13|Rebo Research|Video storage and synchronization|
    JP2882433B2|1992-03-31|1999-04-12|日本ビクター株式会社|Video signal time base correction circuit|
    JPH0686228A|1992-08-31|1994-03-25|Sony Corp|Time base corrector|
    JP3098336B2|1992-10-16|2000-10-16|パイオニアビデオ株式会社|Digital time base collector|
    JPH07177535A|1993-12-16|1995-07-14|Pioneer Video Corp|Digital time base corrector|
    KR0145444B1|1994-11-04|1998-07-15|김광호|Speed control circuit at speed changing for display apparatus|
    US6836295B1|1995-12-07|2004-12-28|J. Carl Cooper|Audio to video timing measurement for MPEG type television systems|
    DE19710270A1|1997-03-13|1998-09-17|Thomson Brandt Gmbh|Method and device for arranging digitized image signals or data in orthogonal rows and columns|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP753855A|JPS5646303B2|1974-12-25|1974-12-25|
    JP5340675A|JPS5654112B2|1975-05-02|1975-05-02|
    [返回顶部]